Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system

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Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system

Authors

Xudong Liao, Shuyi Pan, Zhenxing Zhang, Sainan Huai, Zhiwen Zong, Xiaopei Yang, Kunliang Bu, Wen Zheng, Xinsheng Tan, Yang Yu, Yuan Li, Yi-Cong Zheng, Tianqi Cai, Shengyu Zhang

Abstract

Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.

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